Machine Learning for Circuit Topology Design Automation

In case of analog circuit design, the two important steps are topology design and the determination of device sizes and parameters. The topology of an electronic circuit is the form taken by the network of interconnections of the circuit components. The process of topology design is time consuming and having an unsuitable topology leads to redesign. Even today, automation tools for topology design are still much less explored due to its high degree of freedom.

The three cases where ML is used in topology design are:

1.   Topology Selection

Fuzzy logic is an approach to computing based on "degrees of truth" rather than the usual binaries of 1(true) or 0(false). A fuzzy logic based topology selection tool, FASY, was proposed in 1996. It uses fuzzy logic to describe relationships between specifications (e.g., DC gain) and alternatives and use backpropagation to train the optimizer.

Along with that CNN (convolutional neural networks) are also used for classification. CNN is trained with circuit specifications as the inputs and the topology indexes as the labels.

One of the drawbacks to using ML in topology selection is that it is efficient only when repetitive design patterns are needed and a pretrained model can be used. Else, the process of training is very time consuming and is not beneficial for every new model.

 

2.  Topological Feature Extraction

To make the complex relationships between components more understandable, we not focus on defining and extracting features from circuit topology. Algorithms for both supervised feature extraction and unsupervised learning of new connections between known building blocks are designed. The algorithms have multiple uses, like finding hierarchical structures, isolation of patterns and recognizing the overlaps among structures.

 

3.  Topology Generation

RNN and Hypernetwork are used to solve the topology generation problem and report better performance than the traditional methods when the inductor circuit length 𝑛 ≥ 4.

Research is still on-going for this use case.

Comments

Post a Comment

Popular posts from this blog

FAST STATIC IR DROP PREDICTION USING MACHINE LEARNING

By Anmol Salvi INTRODUCTION: Logic Synthesis , High Level Synthesis , IR drop estimation and Lithography hotspot detection all fall under one broad category in a way which is Electronic Design Automation and are all related to each other to a certain extent.IR drop constraint is one of the fundamental requirements that is enforced in almost every chip design. However, it’s evaluation ends up taking a large amount of time and also the mitigation techniques for fixing any violations may require a number of iterations. Thus , fast and more importantly accurate IR drop prediction becomes essential for reducing the overall design turnaround time. Very recently, machine learning (ML) techniques have been studied very actively so as to allow for fast IR drop estimation owing to their potential promise and recorded success in a lot of fields. IR drop which is also called as voltage drop, is defined as the deviation of a power supply level from its specification which occurs when current begi...
Read more

Machine Learning for Analog Layout

By Ishan Aphale In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we can use a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. The network learns and mimics designers’ behavior from manual layouts. Experiments show that generated wells have comparable post-layout circuit performance with manual designs on the op-amp circuit. The power of machine learning algorithms ha...
Read more

High Level Synthesis using Linear Regression

Image
High Level Synthesis (HLS) works at the algorithmic level in hardware design systems. HLS tools provide automatic conversion from C/C++/SystemC-based specification to hardware description languages like Verilog or VHDL. It has been inferred that these HLS tools are improving the productivity in customised hardware design systems. In certain cases of HLS, the long synthesis time for each design brings about a restriction on design space exploration (DSE). DSE is the process of finding some design solution which optimally meets the design requirements from a space of tentative design points. This exploration is quite complex considering the various levels of abstraction and the entire process from selection of parameter values to choosing an algorithm and then optimising it. Machine Learning for High Level Synthesis: Machine Learning techniques are applied to improve the performance of HLS tools with 3 major advantages: 1. Fast and accurate result estimation 2. Refining the conventional ...
Read more