Machine Learning in EDA

High Level Synthesis (HLS) works at the algorithmic level in hardware design systems. HLS tools provide automatic conversion from C/C++/SystemC-based specification to hardware description languages like Verilog or VHDL. It has been inferred that these HLS tools are improving the productivity in customised hardware design systems. In certain cases of HLS, the long synthesis time for each design brings about a restriction on design space exploration (DSE). DSE is the process of finding some design solution which optimally meets the design requirements from a space of tentative design points. This exploration is quite complex considering the various levels of abstraction and the entire process from selection of parameter values to choosing an algorithm and then optimising it. Machine Learning for High Level Synthesis: Machine Learning techniques are applied to improve the performance of HLS tools with 3 major advantages: 1. Fast and accurate result estimation 2. Refining the conventional ...

Introduction High level Synthesis tools are greatly used in logic synthesis. The reports from HLS tools provide important guidance for tuning the high-level directives. However, acquiring accurate result estimation in an early stage is difficult due to complex optimizations in the physical synthesis, imposing a trade-off between accuracy (waiting for post-synthesis results) and efficiency (evaluating in the HLS stage). ML can be used to improve the accuracy of HLS reports through learning from real design benchmarks. Estimation of Timing, Resource Usage and Operation Delay: The overall workflow of timing and resource usage prediction is as shown in the following figure. The main methodology is to train an ML model that takes HLS reports as input and outputs a more accurate implementation report without conducting the time-consuming post-implementation. The workflow can be divided into two steps: data processing and training estimation models. Step 1 - Data Processing : To enable ML...

By Ishan Aphale In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we can use a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. The network learns and mimics designers’ behavior from manual layouts. Experiments show that generated wells have comparable post-layout circuit performance with manual designs on the op-amp circuit. The power of machine learning algorithms ha...

By Anmol Salvi INTRODUCTION:-High level Synthesis is a method by which one can realize RTL(Register transfer Level) by taking an algorithmic description as input. The control algorithms are typically written in high level programming languages such as C , OpenCL and SystemC among others. The adoption of HLS however at an industrial level is still at the evaluation stage. There are 2 major bottlenecks that arise from the use of HLS tools:- 1)DSE(Design Space Exploration)-A substantial effort is needed for setting the micro-architecture constraints. 2)The long runtime of such HLS tools.   IMPLEMENTATION:-Before discussing the implementation its is crucial to know how the random forest algorithm works. The Random Forest Algorithm put simply is a supervised learning algorithm that builds multiple decision trees and merges them together to get a more accurate and stable prediction. Moving on to the implementation , two stages exist , the first being the training stage , follow...