Logic Synthesis in VLSI

Logic synthesis is basically a process through which a specification of a desired circuit behavior is turned into or translated into a design implementation in terms of logic gates. This translation of a design representation into a circuit comprising of transistors is known as logic synthesis. It is a major part in any circuit designing for implementation of hardware. This synthesis is generally done by using a computer program called as a synthesis tool. The designs specified in hardware description languages are translated using these synthesis tools. The specification of circuit behavior is typically given at register transfer level. Thus, logic synthesis is basically converting a high-level description of design into an optimized gate-level representation.

The logic synthesis can be majorly summarized in three main points that are translation, optimization and technology mapping.

Translation: In this, the RTL code is translated to a representation which is technology independent. The logic that is converted is then available in a boolean equation form.

Optimization: The obtained Boolean equation is optimized using sum of products (SOP) optimization methods.

Technology mapping: The optimized Boolean equations are then mapped to technology dependent library logic gates based on design constraints and library of available technology gates.

Why perform Logic Synthesis?

There are various advantages of performing logic synthesis.

1. Automatically manages many details of the design process due to which there are fewer bugs and the productivity is also improved.
2. It abstracts the design data that is the description given in HDL from any particular implementation technology. The designs can be re-synthesized targeting various chip technologies.
E.g: first implement in FPGA then later in ASIC
3. In some cases, leads to a more optimal design than could be achieved by manual means (logic optimization)

Logic Synthesis Flow




RTL description:
It basically describes the design at a high level using Register Transfer Level constructs.

Translation:
The synthesis tool converts the RTL description to an un-optimized Internal representation, that is we get the Boolean form.

Un-optimized Intermediate Representation:
It is represented internally by the logic synthesis tool in terms of internal data structures.

Logic Optimization:
Logic is optimized to remove redundant logic and use fewer hardware.

Technology Mapping and Optimization:
The synthesis tool takes the internal representation and implements the representation in gates, using the cells provided in the technology library.

Technology Library:
It consists of library cells that can be basic gates or macro cells.


Comments

Post a Comment

Popular posts from this blog

FAST STATIC IR DROP PREDICTION USING MACHINE LEARNING

By Anmol Salvi INTRODUCTION: Logic Synthesis , High Level Synthesis , IR drop estimation and Lithography hotspot detection all fall under one broad category in a way which is Electronic Design Automation and are all related to each other to a certain extent.IR drop constraint is one of the fundamental requirements that is enforced in almost every chip design. However, it’s evaluation ends up taking a large amount of time and also the mitigation techniques for fixing any violations may require a number of iterations. Thus , fast and more importantly accurate IR drop prediction becomes essential for reducing the overall design turnaround time. Very recently, machine learning (ML) techniques have been studied very actively so as to allow for fast IR drop estimation owing to their potential promise and recorded success in a lot of fields. IR drop which is also called as voltage drop, is defined as the deviation of a power supply level from its specification which occurs when current begi...
Read more

Machine Learning for Analog Layout

By Ishan Aphale In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we can use a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. The network learns and mimics designers’ behavior from manual layouts. Experiments show that generated wells have comparable post-layout circuit performance with manual designs on the op-amp circuit. The power of machine learning algorithms ha...
Read more

High Level Synthesis using Linear Regression

Image
High Level Synthesis (HLS) works at the algorithmic level in hardware design systems. HLS tools provide automatic conversion from C/C++/SystemC-based specification to hardware description languages like Verilog or VHDL. It has been inferred that these HLS tools are improving the productivity in customised hardware design systems. In certain cases of HLS, the long synthesis time for each design brings about a restriction on design space exploration (DSE). DSE is the process of finding some design solution which optimally meets the design requirements from a space of tentative design points. This exploration is quite complex considering the various levels of abstraction and the entire process from selection of parameter values to choosing an algorithm and then optimising it. Machine Learning for High Level Synthesis: Machine Learning techniques are applied to improve the performance of HLS tools with 3 major advantages: 1. Fast and accurate result estimation 2. Refining the conventional ...
Read more