Reinforcement learning for logic synthesis
By Ishan Aphale Logic synthesis is one of the most important steps in modern chip design, and consequently in EDA. Logic synthesis converts the behavioural level description into gate level description, which is one of the most important problems in EDA. Logic synthesis is the implementation of the specific logic functions by generating a combination of gates selected in a given cell library, and optimizes the design for different goals. Being a complicated process, it cannot be solved perfectly and so heuristic algorithms are widely used in this stage, which include lots of ML methods. The emergence of new technologies and slowing down of Moore’s law is putting increasing pressure on the field of EDA. Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) is dependent on the sequence of optimizations used. Efficient design space exploration is challenging because of the exponential number of possible optimization permutations. T...